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TK3715 data sheet turbo-epon tm soc bridge for china standard onu rev 1.00 confidential - view under nda only features ? 2.5/1.25gbps downstream with auto- detection, 1.25gbps upstream ? ultra low jitter integrated epon serdes (2.5/1.25gbps) ? ieee 802.3ah epon mac ? triple churning key decryption ? china epon standard oam control ? 802.3ah oam control ? independent 10/100 and 10/100/1000 subscriber ports ? 802.3 10/100 mac and 10/100/1000 mac ? mac address learning for up to 64 mac addresses per ethernet port for 802.1d bridging ? highly flexible 802.1q vlan support ? 802.1p/q support ? 40 fully-configurable queues ? 1.5 mb of integrated packet buffering ? line-rate layer 2/3/4 packet classification and filtering for up to 256 entries ? per-port 802.3x flow control ? 802.3ah forward error correction (fec) ? up to eight logical link ids (llid) ? internal management information base (mib) counters for network statistics ? remote monitoring (rmon) statistics ? embedded 80c51 processor with integrated memory ? ieee 1149.1 jtag boundary scan ? low power 3.3v i/o and 1.2v core supply ? 128-pin lqfp with exposed pad, and tfbga-169 packages ? pin compatibility with tk3713 and tk3714 ? industrial temperature operation, -40c to +85c description the TK3715 chip for optical networ k units (onu) is an ieee 802.3ah-compliant system- on-chip (soc) ethernet passive optical network (epon) bridge. the TK3715 supports all the functions needed to comply with the china standard for epon. it provides high-speed, fiber opti c broadband access for residential and business cpe (customer premises equipment) onus. the auto-sensing turbo-epon tm mode operates at 1.25ghz downstream with legacy systems and 2.5ghz downstre am with turbo-epon olts, such as the tk3723. the TK3715 is compatible with all teknovus olt chipsets. t he TK3715 is cost-optimized for markets using the china standard for epon. the high level of integration in the TK3715 greatly simplifies onu design. the TK3715 contains an 802.3ah epon mac, a serdes, line-rate l2/l3/l4 classification and filtering, china epon decryption, forward error correction (fec), integrated packet buffering, two independent subscriber ports and an embedded processor. the proc essor supports a sophisticated onu management system, including alarms, provisioning, dhcp and igmp functions for a stand-alo ne iptv solution at the onu. glueless interfaces are provided for an external epon transceiver, flash and 10/100/1000 phys. the TK3715 can be managed from the olt over the epon using 802.3ah standard oam messaging and china oam extensions. combined with the hardware-based dba of the teknov us olt chipset and the teknovus host interface software, the TK3715 is ideal for onus designed for iptv . this complete epon system solution provides all the necessary low-level management software, allowing devel opers to get new products to market quickly. the TK3715 is offered in low-cost 128-pin low-profile quad flat pack (lqfp) and 169-ball thin and fine pitch ball grid array (tfbga) packages. the tfbga package wi th its 11x11mm body size is ideally suited for sfp applications. http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu rev 1.00 confidential - view under nda only TK3715 (onu) optical burst transceiver pon uni db9 serial flash (1m x 8) tbi_upen 10/100 phy mii mii/ gmii/ tbi rj45 magnetics port 2: 10/100base-t ethernet (copper) rj45 magnetics port 1: 10/100/1000base-t ethernet (copper) spi 10/100/1000 phy single fiber figure 1. block diagram of TK3715-based onu http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 3 of 58 rev 1.00 confidential - view under nda only revision history this section records the change history of this data sheet. table 1. revision history date version revision description april 23, 2008 1.00 - initial formal release http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 4 of 58 rev 1.00 confidential - view under nda only table of contents 1 TK3715 pin information ............................................................................................................................... ................. 10 1.1 TK3715 pin descriptions ............................................................................................................................... ...... 12 2 TK3715 functional description ............................................................................................................................... .... 19 2.1 10/100 ethernet mac and 10/100/1000 ethernet mac ....................................................................................... 20 2.2 classification and filtering ............................................................................................................................... .... 21 2.2.1 mac address learning and filtering ...................................................................................................... 22 2.2.2 packet modification ............................................................................................................................... .. 23 2.2.3 static entry filtering ............................................................................................................................... .23 2.2.4 match fields ............................................................................................................................... ............ 23 2.2.5 ipv6 extension header parsing .............................................................................................................. 23 2.2.6 rule levels ............................................................................................................................... .............. 24 2.3 packet buffer configuration ............................................................................................................................... .. 24 2.3.1 connecting queues ............................................................................................................................... .24 2.4 ethernet pon mac ............................................................................................................................... .............. 25 2.5 epon transceiver interface ............................................................................................................................... .26 2.6 reference oscillator ............................................................................................................................... ............. 28 2.7 internal 80c51 processor ............................................................................................................................... ..... 31 2.8 gpio and gpo interface............................................................................................................................... ...... 31 2.9 uart interface ............................................................................................................................... ..................... 33 2.10 ethernet serial management interface (mdio) ................................................................................................... 33 2.11 jtag interface ............................................................................................................................... ..................... 34 2.12 power sequencing and reset ............................................................................................................................. 34 2.13 noise decoupling and power supply recommendations .................................................................................... 35 2.13.1 core logic power supply ....................................................................................................................... 35 2.13.2 i/o power supply ............................................................................................................................... ..... 35 3 TK3715 ac and dc specifications .............................................................................................................................. 3 6 3.1 absolute maxi mum ratings ............................................................................................................................... .. 36 3.2 recommended operating conditions ................................................................................................................. 37 3.3 dc characteristics ............................................................................................................................... ............... 38 3.4 ac characteristics ............................................................................................................................... ................ 39 3.4.1 system and serdes clocks timing ........................................................................................................ 39 3.4.2 local-side mii input timing of the 10/100 ethernet port ........................................................................ 40 3.4.3 local-side mii output timing of the 10/100 ethernet port ..................................................................... 41 3.4.4 local-side mii/gmii input timing of the 10/100/1000 ethernet port ....................................................... 42 3.4.5 local-side mii/gmii output timing of the 10/100/1000 ethernet port .................................................... 43 3.4.6 local-side tbi/gmii input timing ........................................................................................................... 44 3.4.7 local-side tbi/gmii output timing ........................................................................................................ 45 3.4.8 ethernet serial management timing (mdio) .......................................................................................... 46 3.4.9 serdes timing ............................................................................................................................... ......... 47 3.4.10 spi timing ............................................................................................................................... ............... 48 3.4.11 reset and clk_25 timing ...................................................................................................................... 49 4 TK3715 physical dimensions ............................................................................................................................... ....... 50 4.1 lqfp-128 package ............................................................................................................................... .............. 50 4.1.1 lqfp-128 exposed pad pcb design guidelines ................................................................................... 52 http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 5 of 58 rev 1.00 confidential - view under nda only 4.2 tfbga-169 package ............................................................................................................................... ........... 55 5 TK3715 ordering information ............................................................................................................................... ....... 57 list of tables table 1. revision history ................................................................................................................................................. 6 table 2. local-side 10/100/1000 mii/gmii/tbi interface (port 1) .................................................................................. 12 table 3. local-side 10/100 mii interface (port 2) .......................................................................................................... 14 table 4. mdio interface ............................................................................................................................... .................. 14 table 5. ethernet pon transceiver serial interface ...................................................................................................... 15 table 6. uart interface ............................................................................................................................... ................. 15 table 7. reference clocks and global reset ................................................................................................................ 15 table 8. jtag interface ............................................................................................................................... .................. 16 table 9. gpio interface ............................................................................................................................... .................. 16 table 10. processor bus interface ............................................................................................................................... .... 17 table 11. test and configuration interface ...................................................................................................................... 17 table 12. digital power and ground ............................................................................................................................... .17 table 13. internal serdes power ............................................................................................................................... ...... 18 table 14. ipv6 next header ............................................................................................................................... .............. 23 table 15. jtag instructions and operations ................................................................................................................... 34 table 16. absolute maxi mum ratings ............................................................................................................................. 36 table 17. recommended operating conditions .............................................................................................................. 37 table 18. dc characteristics ............................................................................................................................... ............ 38 table 19. system and serdes reference clocks timing ................................................................................................ 39 table 20. local-side mii input timing of the 10/100 ethernet port .................................................................................. 40 table 21. local-side mii output timing of the 10/100 ethernet port ............................................................................... 41 table 22. local-side mii/gmii input timing of the 10/100/1000 ethernet port ................................................................ 42 table 23. local-side mii/gmii output timing of the 10/100/1000 ethernet port ............................................................. 43 table 24. local-side tbi input timing ............................................................................................................................. 44 table 25. local-side gmii input timing ........................................................................................................................... 44 table 26. local-side tbi/gmii output timing ................................................................................................................. 45 table 27. ethernet serial management timing ................................................................................................................ 46 table 28. serdes output timing ............................................................................................................................... ....... 47 table 29. serdes input timing ............................................................................................................................... ......... 47 table 30. spi timing ............................................................................................................................... ........................ 48 table 31. reset and clk_25 timing ............................................................................................................................... 49 table 32. lqfp-128 package dimensions ...................................................................................................................... 51 table 33. tfbga-169 package dimensions ................................................................................................................... 56 list of figures figure 1. block diagram of TK3715-based onu .............................................................................................................. 5 figure 2. TK3715 pin diagram in 128-lqfp package .................................................................................................... 10 figure 3. TK3715 ball array in tfbga-169 package ..................................................................................................... 11 figure 4. TK3715 block diagram ............................................................................................................................... ..... 19 figure 5. mii interface with 10/100 ethernet phy ........................................................................................................... 20 http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 6 of 58 rev 1.00 confidential - view under nda only figure 6. fifo interconnection structure ........................................................................................................................ 25 figure 7. fec packet delineation ............................................................................................................................... .... 26 figure 8. serdes typical unfiltered electrical eye diagram ........................................................................................... 27 figure 9. internal serdes connec tion to epon transceiver .......................................................................................... 28 figure 10. differential clock interface ............................................................................................................................... 29 figure 11. single-ended clock interface ........................................................................................................................... 29 figure 12. teknovus loop-timed clock mode .................................................................................................................. 30 figure 13. pll loop-timed clock mode ........................................................................................................................... 30 figure 14. flash memory connections ........................................................................................................................... 31 figure 15. simplified gpio pin block diagram ................................................................................................................. 32 figure 16. sample gpo interface ............................................................................................................................... ...... 32 figure 17. uart interface timing ............................................................................................................................... ...... 33 figure 18. mii serial management read and write timing diagrams .............................................................................. 33 figure 19. device identity register and its fields for idcode instruction ........................................................................ 34 figure 20. power supply filter ............................................................................................................................... ........... 35 figure 21. system and serdes clock timing .................................................................................................................... 39 figure 22. local-side mii input timing of the 10/100 ethernet port .................................................................................. 40 figure 23. local-side mii output timing of the 10/100 ethernet port ............................................................................... 41 figure 24. local-side mii/gmii input timing of the 10/100/1000 ethernet port ................................................................ 42 figure 25. local-side mii/gmii output timing of the 10/100/1000 ethernet port ............................................................. 43 figure 26. local-side tbi input timing ............................................................................................................................. 44 figure 27. local-side gmii input timing ........................................................................................................................... 44 figure 28. local-side tbi/gmii output timing ................................................................................................................. 45 figure 29. mdio timing ............................................................................................................................... ..................... 46 figure 30. serdes output timing ............................................................................................................................... ....... 47 figure 31. spi write timing ............................................................................................................................... ............... 48 figure 32. spi read timing ............................................................................................................................... ............... 48 figure 33. reset and clk_25 timing ............................................................................................................................... 49 figure 34. lqfp-128 package drawing ........................................................................................................................... 50 figure 35. recommended land pattern ........................................................................................................................... 52 figure 36. recommended vias grid dimensions and stencil openings .......................................................................... 53 figure 37. vias and plated hole dimensions .................................................................................................................... 53 figure 38. tfbga-169 package drawing ......................................................................................................................... 55 figure 39. TK3715 ordering information ........................................................................................................................... 57 http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 7 of 58 rev 1.00 confidential - view under nda only 1 TK3715 pin information TK3715 128-lqfp (topview) exposed lead frame vss pin 129 135791113151719212325272931 35 33 37 103 127 125 123 121 119 117 115 113 111 109 107 105 81 79 77 75 73 71 69 67 65 8385 87 89919395 101 99 97 41 43 45 47 49 51 53 55 57 59 61 63 39 vddcore gmii_txd_3 gmii_txd_1 gmii_txd_0 vddio gmii_col gmii_crs vddio vddcore vddio gmii_gtxclk vddcore gmii_txd_7 gmii_txd_6 vddcore vddio gmii_txd_4 gmii_txd_2 vddcore gmii_txd_5 gmii_rxd_0 gmii_rxd_1 gmii_rxd_3 vddcore gmii_rxd_2 gmii_txclk gpio_7 urt_txd1 vddcore vddcore vddcore int_n gpio_5 gpio_4 gpio_6 gpio_3 vddcore rst_n pf_int_n vddio vddcore urt_rxd1 test_mode_n spi_cs_n urt_txd0 vddcore urt_rxd0 gpio_2 gpio_1 vddio spi_din spi_dout figure 2. TK3715 pin diagram in 128-lqfp package http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 8 of 58 rev 1.00 confidential - view under nda only figure 3. TK3715 ball array in tfbga-169 package http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 9 of 58 rev 1.00 confidential - view under nda only 1.1 TK3715 pin descriptions legend: i = input i/o = input/output o/z = output which can be placed in high-impedance state p = power nc = no connect all signal levels are cmos except as noted. all cmos pins contain internal pull-up re sistors. internal pull-up resistors value range between 40k-100kohms. table 2. local-side 10/100/1000 mii/gmii/tbi interface (port 1) lqfp pin tfbga ball signal name i/o signal description 9 k12 gmii_rxclk/ tbi_rbc0 i* this is a triple function pin: ? mii: 25.0/2.5mhz receive clock. generated by phy to clock-in gmii_rxd[3:0], gmii_rxer, and gmii_rxdv ? gmii: 125mhz receive clock. generated by phy to clock-in gmii_rxd[7:0], gmii_rxer, and gmii_rxdv ? tbi: 62.5mhz receive rbc0 clock. generated by serdes to clock-in tbi_rxd[9:0] (odd code) 122 l9 gmii_txclk/ tbi_rbc1 i* this is a dual function pin: ? mii: 25.0/2.5mhz transmit clock. generated by phy to clock-out gmii_txd[3:0], gmii_txer, and gmii_txen ? tbi: 62.5mhz receive rbc1 clock. generated by serdes to clock-in tbi_rxd[9:0] (even code) ? gmii: unused; pull down with 1k- 4.7kohm resistor 124 l10 gmii_rxd0/ tbi_rxd0 i mii/gmii/tbi: receive data [0] from phy/serdes 125 m10 gmii_rxd1/ tbi_rxd1 i mii/gmii/tbi: receive data [1] from phy/serdes 127 n11 gmii_rxd2/ tbi_rxd2 i mii/gmii/tbi: receive data [2] from phy/serdes 128 m11 gmii_rxd3/ tbi_rxd3 i mii/gmii/tbi: receive data [3] from phy/serdes 2 n12 gmii_rxd4/ tbi_rxd4 i this is a dual function pin: ? gmii/tbi: receive data [4] from phy/serdes ? mii: unused; leave unconnected (nc) 3 m12 gmii_rxd5/ tbi_rxd5 i this is a dual function pin: ? gmii/tbi: receive data [5] from phy/serdes ? mii: unused; leave unconnected (nc) 4 k11 gmii_rxd6/ tbi_rxd6 i this is a dual function pin: ? gmii/tbi: receive data [6] from phy/serdes ? mii: unused; leave unconnected (nc) http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 10 of 58 rev 1.00 confidential - view under nda only lqfp pin tfbga ball signal name i/o signal description 5 m13 gmii_rxd7/ tbi_rxd7 i this is a dual function pin: ? gmii/tbi: receive data [7] from phy/serdes ? mii: unused; leave unconnected (nc) 7 l12 gmii_rxdv/ tbi_rxd8 i this is a dual function pin: ? mii/gmii: receive data valid from phy ? tbi: receive data [8] from serdes 8 j11 gmii_rxer/ tbi_rxd9 i this is a dual function pin: ? mii/gmii: receive data error from phy ? tbi: receive data [9] from serdes 121 n9 gmii_crs/ tbi_comma i this is a triple function pin: ? mii: carrier sense. indicates when the line is busy ? tbi: comma. indicates valid comma detected. if not available then pull up this input with 10kohm resistor ? all other modes: unused; leave unconnect ed (nc) (gmii is full-duplex only) 120 m9 gmii_col i this is a dual function pin: ? mii: collision. in half-duplex mode, indicates a collision ? all other modes: unused; leave unconnect ed (nc) (gmii is full-duplex only) 117 m8 gmii_gtxclk/ tbi_txclk o this is a triple function pin: ? gmii: 125mhz transmit clock. used by gigabit phy for clocking-in gmii_txd[7:0], gmii_txer, and gmii_txen ? tbi: 125mhz transmit/reference clock. used by serdes for clocking-in tbi_txd[9:0] ? mii: unused; leave unconnected (nc) 115 l8 gmii_txd0/ tbi_txd0 o mii/gmii/tbi: transmit data [0] to phy/serdes 114 m7 gmii_txd1/ tbi_txd1 o mii/gmii/tbi: transmit data [1] to phy/serdes 112 m6 gmii_txd2/ tbi_txd2 o mii/gmii/tbi: transmit data [2] to phy/serdes 111 l6 gmii_txd3/ tbi_txd3 o mii/gmii/tbi: transmit data [3] to phy/serdes 108 m5 gmii_txd4/ tbi_txd4 o this is a dual function pin: ? gmii/tbi: transmit data [4] to phy/serdes ? mii: unused; leave unconnected (nc) 107 l5 gmii_txd5/ tbi_txd5 o this is a dual function pin: ? gmii/tbi: transmit data [5] to phy/serdes ? mii: unused; leave unconnected (nc) 105 m4 gmii_txd6/ tbi_txd6 o this is a dual function pin: ? gmii/tbi: transmit data [6] to phy/serdes ? mii: unused; leave unconnected (nc) 104 n3 gmii_txd7/ tbi_txd7 o this is a dual function pin: ? gmii/tbi: transmit data [7] to phy/serdes ? mii: unused; leave unconnected (nc) http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 11 of 58 rev 1.00 confidential - view under nda only lqfp pin tfbga ball signal name i/o signal description 101 l4 gmii_txen/ tbi_txd8 o this is a dual function pin: ? mii/gmii: transmit data enable to phy ? tbi: transmit data [8] to serdes 100 n2 gmii_txer/ tbi_txd9 o this is a dual function pin: ? mii/gmii: transmit data error to phy ? tbi: transmit data [9] to serdes * when not used, pull down unused clock inputs with the 1k-4.7kohm resistors, and leave all other pins unconnected. table 3. local-side 10/100 mii interface (port 2) lqfp pin tfbga ball signal name i/o signal description 28 e12 mii_rxclk i* receive clock. generated by phy to clock-in mii_rxd[3:0], mii_rxer, and mii_rxdv 30 d11 mii_rxd0 i receive data [0] from 10/100 phy to TK3715 31 d12 mii_rxd1 i receive data [1] from 10/100 phy to TK3715 32 c13 mii_rxd2 i receive data [2] from 10/100 phy to TK3715 33 c12 mii_rxd3 i receive data [3] from 10/100 phy to TK3715 27 e13 mii_rxdv i receive data valid. signal s the presence of data on mii_rxd[3:0] 25 e11 mii_rxer i receive error. indica tes a transmit coding error has occurred 21 g11 mii_crs i carrier sense. indicates when the line is busy 22 f13 mii_col i collision. in half-duplex mode, indicates a collision 24 f11 mii_txclk i* transmit clock. generated by phy to clock-out mii_txd[3:0], mii_txer, and mii_txen 16 h13 mii_txd0 o transmit data [0] from TK3715 to phy 17 h11 mii_txd1 o transmit data [1] from TK3715 to phy 19 g12 mii_txd2 o transmit data [2] from TK3715 to phy 20 f12 mii_txd3 o transmit data [3] from TK3715 to phy 14 h12 mii_txen o transmit data enable. si gnals the presence of data on mii_txd[3:0] 13 j13 mii_txer o transmit data error * when not used, pull down both clock inputs with the 1k-4.7kohm resistors, and leave a ll other pins unconnected (nc). table 4. mdio interface lqfp pin tfbga ball signal name i/o signal description 10 k13 mdio_data i/o management data i/o. serial access for configuration of external phy(s) 11 j12 mdio_clk o management data clock. clo ck for r/w of device configuration register http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 12 of 58 rev 1.00 confidential - view under nda only table 5. ethernet pon transceiver serial interface lqfp pin tfbga ball signal name i/o signal description 82 f1 pad_rxp i* positive receive seri al data from optical transceiver 83 g1 pad_rxn i* negative receive seri al data from optical transceiver 78 e2 pad_txn o* negative transmit serial data to optical transceiver 79 f2 pad_txp o* positive transmit serial data to optical transceiver 89 j2 ser_atb_0 o 90 h3 ser_atb_1 o serdes analog test bus. for internal testing only; do not connect (nc) for normal operation 85 h2 pad_rext i external reference resistor . connect through a 5kohm (+/-1%) resistor to ground 92 k2 tbi_upen o laser enable to epon optical transceiver 87 h1 pad_ref_clk_p i** positive upstream clock reference from external vco or oscillator (tj p-p < 40ps) 88 j1 pad_ref_clk_n i** negative upstream clock re ference from external vco or oscillator (tj p-p < 40ps) 71 d2 ups_clk_out o internal clock output. for in ternal testing only; do not connect (nc) for normal operation 69 c2 tbi_upd_clk o alternate gmii/tbi 125mhz tran smit clock. this pin can be used instead of gmii_gtxclk/tbi_txclk pin * this interface is non-standard pecl. refer to section 3.3: dc characteristics . ** this lvpecl interface is internally terminated. ac coupli ng capacitors are recommended. pad_ref_clk_n may be tied off to 1.2 v..1.3v reference voltage for single-ended operation. refer to section 2.6: reference oscillator for more details. table 6. uart interface lqfp pin tfbga ball signal name i/o signal description 48 a8 urt_rxd0 i uart serial input data port 0 47 b8 urt_txd0 o uart serial output data port 0 44 a10 urt_rxd1 i uart serial input data po rt 1 (debug mode only); leave unconnected (nc) for normal operation 45 b9 urt_txd1 o uart serial output data port 1 (debug mode only); leave unconnected (nc) for normal operation table 7. reference clocks and global reset lqfp pin tfbga ball signal name i/o signal description 94 k3 clk_125 i 125.0 mhz reference clock (+/-100ppm) 35 b13 clk_25 o 25.0 mhz output reference cl ock. this clock may be used to drive the ethernet phy(s) http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 13 of 58 rev 1.00 confidential - view under nda only lqfp pin tfbga ball signal name i/o signal description 68 b1 clk_125_sel i clock mode configuration. when se t high (1), the core clock will operate off of the clk_125. when set low (0), the core clock will operate off of the pad_ref_clk_p/n inputs. refer to section 2.6: reference oscillator for more details on clocking options. 52 b7 rst_n i system reset (active low) table 8. jtag interface lqfp pin tfbga ball signal name i/o signal description 95 l1 tdi i jtag test data input leave unconnected (nc) for normal operation 97 m3 tms i jtag test mode select leave unconnected (nc) for normal operation 98 m1 tck i jtag clock leave unconnected (nc) for normal operation 96 l2 trstn i jtag test reset (active low) pull down with 1k-4.7kohm to disable jtag functionality 99 m2 tdo o jtag test data output table 9. gpio interface lqfp pin tfbga ball signal name i/o signal description 65 c4 gpio0 i/o general purpose i/o [0] (default input) 63 a3 gpio1 i/o general purpose i/o [1] (default input) 62 b4 gpio2 i/o general purpose i/o [2] (default input) 61 c5 gpio3 i/o general purpose i/o [3] (default input) 58 b5 gpio4 i/o general purpose i/o [4] (default input) 57 a5 gpio5 i/o general purpose i/o [5] (default input) 55 b6 gpio6 i/o general purpose i/o [6] (default input) 54 a6 gpio7 i/o general purpose i/o [7] (default input) 37 a12 gpio8 i/o general purpose i/o [8] (default input) 36 b12 gpio9 i/o general purpose i/o [9] (default input) 74 d1 gpio10 i/o general purpose i/o [10] (default input) 73 d3 gpio11 i/o general purpose i/o [11] (default input) 66 b2 gpo_so o general purpose shift data output 67 b3 gpo_clk o general purpose shift clock http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 14 of 58 rev 1.00 confidential - view under nda only table 10. processor bus interface lqfp pin tfbga ball signal name i/o signal description 49 c8 int_n i processor interrupt (active low) 53 c6 pf_int_n i when trstn pin is low (0), this is power failure interrupt input to 80c51 processor (active low) 39 c10 spi_din i serial flash memory data to the TK3715 40 a11 spi_dout o serial flash memory data from the TK3715 42 c9 spi_cs_n o serial flash memory chip select (active low) 38 b11 spi_sclk o serial flash memory clock (default 15.625mhz) table 11. test and configuration interface lqfp pin tfbga ball signal name i/o signal description 76 e1 sm_n i ic scan test mode enable (active low). pull up for normal operation 41 b10 test_mode_n i test mode enable (active low). pull up for normal operation table 12. digital power and ground lqfp pin tfbga ball signal name i/o signal description 6, 18, 29, 46, 64, 70, 93, 106, 113, 116, 123 a2, a9, c1, d13, g13, k1, l13, n4, n6, n7, n10 vddio p 3.3 v i/o supply voltage 1, 12, 15, 23, 26, 34, 43, 50, 51, 56, 59, 60, 72, 77, 91, 102, 103, 109, 110, 118, 119, 126 a1, a4, a7, a13, d4, d5, d6, d7, d8, d9, d10, e4, e10, f4, f10, g4, g10, h4, h10, j4, j10, k4, k5, k6, k7, k8, k9, k10, n1, n5, n8, n13 vddcore p 1.2 v core supply voltage 129 (exposed pad*) c3, c7, c11, e3, e5, e6, e7, e8, e9, f5, f6, f7, f8, f9, g5, g6, g7, g8, g9, h5, h6, h7, h8, h9, j3, j5, j6, j7, j8, j9, l3, l7, l11 vss p ground supply (also thermal pad in lqfp package) 75 - gnd p ground (test mode) * this is the main vss ground connection in lqfp-128 package. ensu re sufficient current return path and thermal connectivity fo r the entire ic. refer to section 4.1.1: lqfp-128 exposed pad pcb design guidelines for more details. http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 15 of 58 rev 1.00 confidential - view under nda only table 13. internal serdes power lqfp pin tfbga ball signal name i/o signal description 80, 81 f3 pad_vdd p* serdes vdd 1.2v supply 86 g3 pad_vdda p* serdes analog vdd 1.2v supply 84 g2 pad_vdd33 p* serdes vdd 3.3v supply * each pin should be filtered individually. refer to section 2.13.2: i/o power supply . ?ripple? noise amplitude must be limited to less than 50mv (peak-to-peak for 50khz..100mhz frequencies). http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 16 of 58 rev 1.00 confidential - view under nda only 2 TK3715 functional description the TK3715 is an ieee 802.3ah stan dard ethernet pon (epon) to 10/10 0 and 10/100/1000 ethernet bridge for optical network unit (onu) applications. the TK3715 incorporates an epon mac, an 802.1d bridge, a switching element, and a 10/100 ethernet mac and a 10/ 100/1000 ethernet mac for subscriber access. an integrated processor in the TK3715 provides an embedded management system, including configuration, self management, and auto discovery. together, the TK3715 o nu chip, the teknovus olt chips, and the teknovus host interface software provide a complete epon solution. the two media access controllers (one 10/100 ethernet mac and one 10/ 100/1000 ethernet mac) support half- duplex and full-duplex operation for end user traffic. three ethernet lookup engines (lues) enable traffic prioritization, local address filtering, and statistics gathe ring. twenty internal fifos provide buffering for upstream and downstream traffic and oam traffic. the 80c51 proces sor provides management control. it responds to in- band oam commands and host interface messages for config uration and statistics gathering. refer to figure 4. gpo interface 80c51 cpu 802.3ah mac fifo block epon lookup engine sram (256kb) uni spi sec gigabit ethernet lookup engine 10/100/1000 mac mii/ gmii/ tbi (port 1) ethernet lookup engine 10/100 mac mii (port 2) uart pon tbi_upen gigabit serdes management interface tbi gpio interface 12 upstream sram mdio serial flash fec downstream sram sr (leds) figure 4. TK3715 block diagram http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 17 of 58 rev 1.00 confidential - view under nda only 2.1 10/100 ethernet mac and 10/100/1000 ethernet mac the TK3715 contains two ieee 802.3-compliant ether net macs: one 10/100 mac an d one 10/100/ 1000 gigabit mac. both half-duplex and full-duplex modes of oper ation are supported for the 10/100 mac. full-duplex operation is supported for the 10/10 0/1000 mac. rmon statistics ar e gathered for both interfaces. the 10/100 ethernet mac interfaces to an external phy via a standard mii interface. refer to figure 5. the 10/100/1000 ethernet mac connects to an external phy via an mii/gm ii interface, or to an external gigabit serdes via a tbi interface. both macs discard frames based on invalid crc-32 checks ums. if they are configured for 802.3x flow control operation, the macs filter inco ming 802.3x mac control frames. a standard mdio interface is provided to cont rol external phys and/or ethernet switches. figure 5. mii interface with 10/100 ethernet phy http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 18 of 58 rev 1.00 confidential - view under nda only 2.2 classification and filtering there are three types of ethernet looku p engines (lues). each lue corresponds to one of the interface ports: ? the gigabit lookup engine (glu), for incoming et hernet data from port 1 (10/100/1000 interface). ? the ethernet lookup engine (elu), for incoming ethernet data from port 2 (10/100 interface). ? the downstream lookup engine (dlu), for in coming ethernet data from the epon mac port. the lues are configurable via the host interface. refer to the onu host interface specification for programming details. the lues provide source address lear ning, local address filter ing, and static rule filtering on the incoming ethernet data. each ethernet port cont ains a single lookup table sram of 256 entries. this table stores both the dynamic (learned) and static filtering entries. each et hernet port supports up to 64 learned addresses. the remaining table locations are used for static entries. if auto learning is not enabled, all entries are available for static entries. the lues provide line rate classification and filtering for layer 2, layer 3, and lay er 4 packets. the supported fields include the following: ? mac sa/da ? vid ? vlan cos ? ipv4/ipv6 sa/da ? ipv4/ipv6 priority field ? tcp/udp source/destination port new fields can be defined by the operator. the classifica tion rules can also be re-configured by the operator. each destination fifo is mapped to a strict priority scheduler, as follows: ? in the upstream direction, the onu supports one strict priority scheduler per logical link. ? in the downstream direction, the onu supports on e strict priority scheduler per ethernet port. up to 8 rules can be combined to support complex classification operations, using a boolean and condition. for example: if ((ipv4sa >= 192.168.200.1) and (ipv4sa <= 192.168.200.20) and (tos == 3)) send traffic to fifo 4 priority values can be assigned to the rules to prevent conflicts. the numerically lower value receives the higher priority. if one rule has a priority value of 0 and a conflicting rule has a priority value of 14, the 0-value rule will be implemented, and the 14-value rule will be ignored. for example: rule x, priority=14: if (ipv4sa == 192.168.1.100) send traffic to fifo 3 rule y, priority=0: if (vid exists in frame) drop in this example, a frame with vid will be dropped, ev en if the frame?s ipv4 sa is set to 192.168.1.100. http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 19 of 58 rev 1.00 confidential - view under nda only the lues provide the connection from the ethernet ports to the fifo queues. the two upstream lues may not share a destination queue. the destination queue ultimately maps to the llid and quality of service for a flow. it can be selected by a static rule ch ecking the ethernet destination address an d source address, the vlan tag id, the vlan tag service, or the differentiated services field. 2.2.1 mac address learning and filtering the TK3715 supports mac source address (sa) lear ning in the upstream direction. mac address learning prevents unnecessary traffic from being sent to t he olt. the TK3715 does not analyze mac addresses in the downstream direction unless a specific classifi cation or filter rule has been provisioned. mac sa learning is performed by the two upstream lues. the lues build and maintain a table of mac address entries gathered from the sas of incoming frames. the TK3715 supports two learning modes: ? 802.1d learning . when a frame is received with a destinati on address (da) that matches an sa entry in the table, the frame is discarded. ? mac access control . when a frame is received with a destination address (da) that does not match an sa entry in the table, the frame is discarded until the da is learned. only one learning mode can be selected at a time. the learning modes are selected using olt host interface software. both learning modes support two configurab le features for learning new mac addresses: age limit and entry limit . age limit the age limit can be configured to delete mac table entries that are not re-learned in a user-defined time period. values entered in the age limit field are automatically rounded down to the nearest power of 2. for example, if the user enters a value between 64 and 127, the value w ill be rounded down to 64 (which is 2^6). if the user enters a value between 128 and 255, the value will be rounded down to 128 (2^7). the maximum age limit is 2^n * 8.75 ms for n = 0 to 15. the age limit is provisioned in units of 8.75 ms. the minimu m time that an entry will remain in the table is 7/8 of the provisioned time. the maximum time that an entry will remain in the table is the provisioned time. if the age limit is set to 0, aging is not performed. in th is case, entries can be manually cleared or overwritten. they are also removed by the entry limit feature, if it is enabled. entry limit the mac table can be configured to limit the number of entries. for the 802.1d learning mode, the per-port limit can be set to any value from 0 to 64. for the mac acce ss control mode, the per-port limit can be set to any value from 0 to 32. when the mac table reaches the configur ed limit, existing entries are over-written by new entries. existing entries are over-written according to how the age limit feature is configured, as follows: ? age limit is off (set to 0). the entry at the bottom of the lis t is overwritten, according to highest order location. this entry might not have the oldest timestamp. ? age limit is on ( set to a non-0 value). the entry with the oldest timestamp is overwritten. if two or more entries share the oldest timestamp, one of these entries will be overwritten. if the entry limit is set to 0, entry limiting is not performed. in this case, all frames are sent to the olt, regardless of da. http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 20 of 58 rev 1.00 confidential - view under nda only note : additional onu filter rules, if any , will filter corresponding frames when the entry limit feature is disabled. 2.2.2 packet modification the lues provide support for adding and deleting vlan tags from a frame. the table results can set or clear an ?add vlan tag? bit with a rule level associated to this function. the vid and cos fields in the vlan tag can be set as a result in a rule. if two rule s set the vid/cos at the same rule prio rity, the results will be bit wise or?ed together. the ?delete vlan tag? bit allows for the removal of the vlan tag from the frame. a vlan tag must be present in the frame for the ?delete vlan tag? bit to m odify the frame. if a frame has both the add and delete tag set, the old tag will be removed and a new tag will be inserted. 2.2.3 static entry filtering the lookup table can be configured with very simple or ve ry complex rules to discard or classify traffic. these rules allow for selection of layer 2 protocol, layer 2 llc, vlan, ipv4 /v6 header, or udp/tcp header fields. typical fields include the vlan tag id, lay er 2 ethertype, and the tos precedence value. 2.2.4 match fields static entries specify a comparison of a field from the fram e with a value in the rule. the match select for the rule may require that the two values are equal, less than, great er than, or not equal. the existence of a field can also be used as a test condition. for example, the user may w ant to discard all frames without a vlan tag. in this case, the vlan tag is specified as a field, and match sele ct of the rule is ?not present?. when a comparison is specified on a field that is not present in the frame, the comparison will not match. in addition, two bit-test match types are defined: ?m atch bit? and ?match not bit?. these match types are used to test if a single bit within a frame is set or not set. the user sets a single bit in the lookup value. the field selected in the rule is then checked against this bit. for the ?match bit? match type, if the bit set in the lookup value is set in the field, it is considered a match. for the ?match not bit? match type, if the bit set in the lookup value is not set in the field, it is considered a match. one application for this match type is to test if the multicast bit is set in an l2 destination address. 2.2.5 ipv6 extension header parsing in the case of ipv6 extension headers, field 11 is fixed to parse the final next header value. the following next header values are interpreted as extension headers: table 14. ipv6 next header number in previous ?next header? field header contents 0 hop-by-hop options 60 destination options 43 routing 44 fragment 51 authentication http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 21 of 58 rev 1.00 confidential - view under nda only any other ?next header? value is interpreted as the final header (l3 protocol type). its value will be parsed into field 11. 2.2.6 rule levels the lues provide 16 levels of rule priority for the tw o output results. a single packet may match more than one static rule. when this occurs, the rule priority is used to determine the result. lower rule priority numbers take precedence over higher numbers. for example, a static entry may have a level 4 rule that forwards all ip packets, and a level 3 rule that discards packets for ip destination 19 2.168.1.x. in this case, an ip packet with a matching address will be discarded. dynamic entries have a default rule value of 2. dynamic discards can be overridden by programming a static rule with a higher priority. some static filtering rules require multiple fields to be matched. for example, a system may be configured as follows: only tcp/ip packets on port 30, sent to a certai n destination ip address range, can be forwarded. this type of rule can be accomplished by chaining 3 rules toget her. the first rule can match the tcp port number on the layer 2 header, while the second and third rules can match the address and port number. the rules in a rule chain must be written to consecutive lo cations in the lookup table. if all rules in a chain match, the result specified by the final rule in the chain will be executed. note : the number of chained entries can not exceed 8. 2.3 packet buffer configuration the fifo block provides buffering for upstream and do wnstream traffic. the fifo block manages the 20 upstream queues and 20 downstream queues. the 20 upstr eam queues can be configured to send data to the processor or to any llid. the 20 downstream queues can be configured to send data to the processor or to one of the two ethernet ports. the queues are allocated spac e from a pool of six 256kb blocks of internal sram. between one and four of the blocks can be assigned to the downstream queues. the remaining blocks are used for upstream queues. 2.3.1 connecting queues once the 40 logical queues are defined, they must be connected to an input and output port. a queue can not be connected to multiple input sources. packets can be duplicated to two queues in both the upstream and downstream directions. the upstream queue input sources are the two upstream lu e blocks and a transmit buffer from the processor. the result of the lue processing is the destination qu eue number. the lue blocks may feed multiple queues, but the configuration must guar antee that the lues don?t use the same queu e. if a queue is used for upstream packet transmission from the processor buffer, it can not be used by the lue blocks. the upstream queue output destinations are the epon mac and a receive buffer to the processor. within the epon mac, the eight logical link identifiers (llids) are possible destinations. the epon mac configuration allows for an llid to have multiple queues as sources. the downstream queue input sources are the epon ma c and a transmit buffer from the processor. the downstream lookup engine (dlu) determines the mapping from input frame type to downstream queue number. the epon mac can not share a queue destination with the processor buffer. the downstream queue output destinations are the two et hernet macs and a receive buffer to the processor. each queue is configured in the fifo block to se lect a destination. multiple queues can share a single http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 22 of 58 rev 1.00 confidential - view under nda only destination. for example, all 20 downstream queues may be configured to a single ethernet port. when multiple queues are configured for the same desti nation, they are serviced in strict priority. the lowest numbered queue has the highest priority. a single queue can output to eit her the processor or to one or both ethernet ports. when a queue is configured for both ethernet ports, packets are duplicated to both interfaces. refer to figure 6. u x 256kb sram d1 x 256kb sram d2 x 256kb sram upstream queues (20 logical) ethernet lookup #1 ethernet lookup #2 downstream queues (z logical) downstream queues (20-z logical) ethernet mac #1 ethernet mac #2 epon mac (16 llids) epon mac (8 llids) note: u + d1 + d2 < 6 fifo 80c51 cpu figure 6. fifo interconnection structure 2.4 ethernet pon mac the epon mac is responsible for filling grants and genera ting report messages. it is configured via the host interface software or the persona lity section of flash memory. llid index 0 supports reporting as defined in the china standard for epon. the epon mac monitors the 20 upstream fifo queues, in order to create report messages. it maps the 20 upstream fifo queues into priority groups. up to eight priority groups can be config ured. based on these groups, the mac generates ?queue report? values in the report messages. report messages contain two queue sets. the second queue set reports the entire depth of the upstream queues. the first queue set reports queue depth up to a programmable threshold. the epon mac contains a frame length fifo. the frame length fifo tracks the frame length and fifo queue number for frames to be transmitted upstream. the fram e length fifo has two purposes. first, it accumulates http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 23 of 58 rev 1.00 confidential - view under nda only frame length information for all queues mapped to the llid index. (frame length information is accumulated up to the programmable threshold.) second, it enforces priority order when frames are taken from the fifo queues and transmitted upstream. frame lengths are pushed into the fram e length fifo in strict queue priority order. queue 0 is the highest priority. the sum of the frame lengths is accumulated. frame lengths are added to the frame length fifo until adding one more w ould exceed the thre shold. when a grant is filled, entries are removed from the frame length fifo. these entries determine the transmi ssion order. as frames are sent upstream, the frame length fifo is replenished in parallel. at the end of a grant, a report frame is sent if requested by the olt. the epon mac is also responsible for inserting time stamps into the epon managem ent frames generated by the host processor. the epon mac provides decryption for downstream tra ffic. the mac uses china standard decryption (triple churning). decryption is performed on a per lli d basis. firmware manages the key exchange. the epon mac generates an 8-byte frame preamble that incl udes the llid of the link and security key selection. the preamble is covered by a crc8 as defined in ieee 802.3ah. the inter- packet gap is 9 6ns for 1gbps epon and 64ns for 2gbps epon. the TK3715 supports 802.3ah forward error correction (fec). frames are delineated by detecting the s_fec and t_fec characters. a hamming code is used to detect th e first match with n number of bits of the expected delineator. idle pattern s_fec preamble data parity t_fec_o/ t_fec_e t_fec_e idle pattern delineator end of data start of parity delineator start of packet delineator end of parity figure 7. fec packet delineation the fec then uses the reed solomon (255, 239) code to correct up to 8 bit errors per block of data. the receiver can receive both fec and non-fec encoded fr ames. the transmitter may be set to transmit fec or non-fec encoded frames. note : the performance of the fec may vary based on the ch oice of optics and error distribution into the serdes. fec adds between 15us and 25us of additional latency to the data path. 2.5 epon transceiver interface the TK3715 contains an ultra-low jitter, integrated 2. 5gbps/1.25gbps serdes. the serdes provides a direct connection to an epon optical transceiver. the serdes has the following features: ? clock and data recovery (cdr) and de-serialization on downstream ? serialization on upstream ? 8b/10b encoding and decoding ? 50? impedance support ? various loop-back functions ? auto self-test http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 24 of 58 rev 1.00 confidential - view under nda only figure 8. serdes typical unfiltered electrical eye diagram the integrated serdes can be connected directly to the epon transceivers using the recommended circuit in figure 9. traces from the TK3715 to the transceiver must have cont rolled impedance. traces must be routed as differential pairs with no stubs and a minimum number of vias. termin ation networks should be located as close to the input pins as possible. all resistors should be 1%. http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 25 of 58 rev 1.00 confidential - view under nda only TK3715 onu burst transceiver pad_tx_p pad_tx_n pad_rx_p pad_rx_n tbi_upen rx + rx - tx + tx - bias 0.01uf 0.01uf 0.01uf 0.01uf 3v3 3v3 130 82 3v3 130 82 3v3 82 130 82 130 1k bias this signal to ?laser off? by default (shown active high bias) figure 9. internal serdes connection to epon transceiver the tbi_upen signal enables the pon transceiver for ups tream transmission. polarity and timing of this signal are programmable. refer to the onu host interface s pecification for details on programming this signal. note : teknovus recommends that the default state of this signal be controlled during power-up and reset. this is done by forcing the optical transceiver into the off state (no light being transmitted in the upstream direction). this will prevent unsolicited burst s of light on the epon network. some optical transceivers have optional connections for presence detect, signal detect, receive signal strength, i 2 c control, etc. these signals may be routed to the gp io pins, if desired. refer to the onu host interface specification for details on how to connect and control these pins. 2.6 reference oscillator the TK3715 requires at least one 125.00mhz reference clock source. in the case of a single oscillator solution, there are two options: the lvpecl diffe rential oscillator (figur e 10) and the single-ended oscillator (figure 11). pad_ref_clk_p/n inputs require either differential lvpecl (figure 10) or a single-ended lvttl source (figure 11). the optional clk_125 input accepts lvttl-type signals only. both clock solutions require a high quality 125.00mhz (+/-100ppm or better) low jitter (tj < 40ps random + deterministic) oscillator. differentia l oscillators provide th e best performance due to their enhanced jitter performance. recommended parts for a single-ended solution include: ? ecliptek ec2600etts-125.000m or eh2600etts-125.000m ? ecs ecs-3953m-1250-bn http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 26 of 58 rev 1.00 confidential - view under nda only ? mf electronics t3392-125m optionally, single-ended oscill ator signals can be ?translated? with an lvttl-to-lvpecl converter ic, and connected to TK3715 pad_ref_clk_p/n inputs. jitter performance of the built-in serd es depends heavily on the quality of the reference clock. therefore, it is important to select a high quality oscillator with good jitter characte ristics. single-ended oscillators provide an economical solution. refer to figure 11. note : teknovus requires that programmable crystal oscillators are not used in this application. figure 10. differential clock interface figure 11. single-ended clock interface http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 27 of 58 rev 1.00 confidential - view under nda only the TK3715 supports two methods of loop-timing on the pon. the first method uses the teknovus loop-time mode. refer to figure 12. this approach minimizes horizontal eye jitter and minimizes cost by eliminating an external cdr/pll. figure 12. teknovus loop-timed clock mode the second method uses true loop timing, with an external serdes for receive clock re covery and jitter reduction. refer to figure 13. in both the figure 12 and figure 13 solutions, either a single-ended interface or a differential interface can be used for the pad_ref_clk_p/n signal. note : only the differential interface is shown. figure 13. pll loop-timed clock mode http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 28 of 58 rev 1.00 confidential - view under nda only 2.7 internal 80c51 processor the 80c51 processor is responsible for running teknovus onu firmware. it provides management (control-path) functionality, but is not required for data-path packet processing. the 80c51 requires external flash memory connected by a serial spi interface. it requires 1mb of flash memory. larger flash chips are supported. however, the extra memory will not be used. the 80c51 reads its firmware program and default onu configuration data from the flash. the TK3715 provides internal 256k x 8 sram. the sram is used as program memory for the 80c51 processor, and not for packet buffering. a glueless interface is also provided for a standard 1m x 8 serial flash memory. the teknovus host interface software is stored with the configuration data in the flash. the flash memory must be capable of operating at l east 16mhz clock rate and hav e 64kb sectors/blocks that are erasable with d8(hex) command. the following 8mbit serial flash memories are currently supported by teknovus firmware: ? nexflash nx25p80-v ? winbond w25p80-v, w25p16-v, w25x80v ? st micro m25p80-v ? macronix mx25l8005 ? eon silicon en25p80, en25f80. figure 14. flash memory connections 2.8 gpio and gpo interface twelve uncommitted gpio pins are provided in the TK3715. a serial gpo interface is also provided. gpio pins can be programmed as inputs or outputs. refer to fi gure 15. gpio and gpo pins are programmable via the personality editor application. note : teknovus does not recommend sinking or sourcing more than 8ma on any gpio pin. http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 29 of 58 rev 1.00 confidential - view under nda only figure 15. simplified gpio pin block diagram the gpo interface is used with a serial shift register to drive leds. acceptable shift registers include the ti cd74ac164 8-bit shift register. up to 16 serial regist ers may be used externally. the hardware will shift out when updates are made to the internal register. t he gpo may toggle outputs during shift cycles, and is recommended primarily for leds. the hardware also has the option to ?flash? the leds at a visible rate. refer to figure 16. figure 16. sample gpo interface http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 30 of 58 rev 1.00 confidential - view under nda only 2.9 uart interface the TK3715 provides two uart interfaces. the first interface enables debugging, and provides command line access to the onu. the second uart in terface is used for host monitor and emulator modes, and should be left unconnected. the baud rate is generated from the 125.00mhz referenc e oscillator. an external rs-232 buffer, such as the maxim max3222e, can be used to connect to a standar d rs-232 connector. the teknovus host interface software default line settings are as follows (refer to figure 17): ? baud rate 9600 ? no-parity ? 8 bit data ? 1 stop bit the first pin, uart_dout, refers to uart transmit da ta (output) from the TK3715. the second pin, uart_din, refers to uart receive data (input) to the TK3715. t he uart interface is asynchronous; it does not include any clock. return to idle or start bit of new character baud rate = 9600 start uart_din/ uart_dout d0 d1 d2 d3 d4 d5 d6 d7 stop idle figure 17. uart interface timing 2.10 ethernet serial management interface (mdio) the ethernet serial management interface (mdio) consists of a data interface, basic register set, and a serial management interface to the register set. through this inte rface, it is possible to control and configure multiple phy devices, gather status an d error information, and determine the type and cap abilities of the attached phy devices. figure 18. mii serial management read and write timing diagrams http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 31 of 58 rev 1.00 confidential - view under nda only 2.11 jtag interface a standard jtag interface is provided for in-circuit te sting. during normal TK3715 operation, jtag is not functional. all jtag pins should be pulled high except for the trstn pin. the trstn pin should be pulled low during normal TK3715 operation. trstn and jtag_sel pins should be pulled high during TK3715 jtag operation. please contact teknovus for programming details. teknovus offers a 4-bit in struction register that supports ieee 1149.1 mandatory inst ructions, bypass, extest and sample/preload. in addition, idcode and clamp instructions are supported. chip identity and the manufacturer?s identity can be read using the jtag interface. refer to table 15 for support ed instructions and their operation codes. table 15. jtag instructions and operations code instruction selected register result 0000 extest bsr outputs cells apply their values to ports. input cells sample values on ports. captures 32-bit identity with following fields. bits field decimal hex 0 default value 1 0x1 1:11 teknovus identity 515 0x203 12:27 part number 3714* 0x0e82 0001 idcode device identity 28:31 part version 1 0x0001 0010 sample/ preload bsr sets up boundary scan cells to either sample values moving in or out of devices, or to preload the known values in boundary scan cells prior to the next operation. 0011 clamp bsr + bypass first preset values in output cells ar e taken to output ports. bypass register is then selected between tdi and tdo pins. 0100 to 1111 bypass bypass tdo pin gets the value of tdi pin on clock, all logic is bypassed. * indicates an error for which an errata sheet has been issued. table 15 shows the idcode instruct ion illustration. the lsb (bit-0) for the 32 -bit device identity register will always be ?1?. part numbe r 0x0e82 (3714) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 teknovus jedec identity 0x203 version 0x0001 figure 19. device identity register and its fields for idcode instruction 2.12 power sequencing and reset the 3.3v power supply should be brought up ahead of the 1.2v power supply. this prov ides proper biasing of the esd protection diodes. the rst_n input must be held low for >100ms after the power supplies have stabilized. this allows the crystal oscillators to stabilize and all in ternal circuitry to initialize before code execution begins. http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 32 of 58 rev 1.00 confidential - view under nda only 2.13 noise decoupling and power supply recommendations a multilayer pcb structure is recommended to limit power s upply ?ripple? noise. this structure will also prevent signal noise coupling through power planes. the most im portant capacitor is the capacitance between the ground and power layers in the pcb itself. teknovus recommends putting the power and ground planes next to each other in the middle of the board with minimal spacing (<4.0mils). this increases capacitive coupling between the power and the ground planes, which filter s noise from power planes to ground. note : all ground pins (including analog and thermal) sh ould be tied together through a common system ground plane(s). do not insert any inductor or ferrite bead between analog and digital ground planes. 2.13.1 core logic power supply the core circuitry for the TK3715 operates at 1.2v. the po wer supply for core circuitry does not require any special filtering. note : teknovus recommends that you de-couple as many vddcore pins as possible with a pair of 0.1uf and 0.01uf capacitors. the placement of each pair of capacitors is critical. they should be mounted as closely as possible to the de-coupled pin. the 0.01uf on the smaller value capacitor should be as close to the device as possible. 2.13.2 i/o power supply most of the TK3715 i/o pins operate at 3.3v. the power supply for i/o buffers does not require any special filtering. note : teknovus recommends that each of the 11 vddio pi ns is de-coupled with a pair of 0.1uf and 0.01uf capacitors. the placement of each pair of capacitors is cr itical. they should be mounted as closely as possible to the de-coupled pin. the 0.01uf on the smaller value capacitor should be as close to the device as possible. figure 20. power supply filter http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 33 of 58 rev 1.00 confidential - view under nda only 3 TK3715 ac and dc specifications 3.1 absolute maximum ratings table 16. absolute maximum ratings parameter symbol conditions min max unit v dd1.2 vddcore, pad_vdd/vdda -0.25 1.32 v power supply voltage v dd3.3 vddio, pad_vdd33 -0.25 3.60 v storage temperature t stg - -65 150 oc junction temperature t jmax - -40 125 oc voltage applied to any input pin v pin undershoot/overshoot < 20% of the cycle on vss/vdd -0.25 vdd + 0.25 v power dissipation p max zero air flow - 2000 mw i/o latch-up current i latchup - -200 200 ma esd voltage at any pin v esd(hbm) human body model -2.0 2.0 kv electrostatic discharge this device can be damaged by esd. teknovus recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper hand ling and installation procedures may adversely affect reliability of the device. http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 34 of 58 rev 1.00 confidential - view under nda only 3.2 recommended operating conditions table 17. recommended operating conditions parameter symbol conditions min typ max unit v dd1.2 25oc 1.14 1.20 1.26 v supply voltage v dd3.3 25oc 3.14 3.30 3.46 v supply voltage noise v dd peak-to-peak (50khz-100mhz) - - 50 mv operating ambient temperature t a - -40 25 85 oc operating junction temperature t j - -30 70 110 oc thermal resistance junction to ambient for lqfp-128 ja * jedec 2-layer pcb with no air flow - - 19.9 oc/w thermal resistance junction to ambient for tfbga-169 ja * jedec 4-layer pcb with no air flow - - 20.8 oc/w thermal resistance junction to case for lqfp-128 jc ** jedec with no air flow - - 10.7 oc/w thermal resistance junction to case for tfbga-169 jc ** jedec with no air flow - - 4.3 oc/w p vddio 25oc, 3.3v - 115 250 mw p vddcore 25oc, 1.2v - 420 750 mw 25oc, 1.2v (pad_vdd/vdda) - 130 170 mw p vdd_serdes 25oc, 3.3v (pad_vdd33) - 60 100 mw power dissipation*** p d 25oc - 725 1270 mw * ja = (t j ? t a )/p max ** jc = (t j ?t c )/p top where p top is power dissipation from the top of the package *** for 1.25gbps and 2.5gbps rx rates http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 35 of 58 rev 1.00 confidential - view under nda only 3.3 dc characteristics table 18. dc characteristics parameter symbol conditions min typ max unit i dd3.3 25oc, 3.3v - 52 - ma supply current i dd1.2 25oc, 1.2v - 460 - ma cmos input high voltage v ih 25oc 2.00 - 3.60 v cmos input low voltage v il 25oc -0.30 - 0.80 v cmos output high voltage v oh 25oc 2.40 - - v cmos output low voltage v ol 25oc - - 0.40 v cmos input leakage current i i v i = 3.3v or 0v - - 10 ua cmos tri-state output leakage current i oz v oz = 3.3v or 0v - - 10 ua cmos output high current i oh c load = 50pf @ v oh = 2.4v 5.8 9.5 13.3 ma cmos output low current i ol c load = 50pf @ v ol = 0.4v 4.7 9.9 16.9 ma pad_rxp/n inputs differential voltage v id differential (peak-peak) 400 - 1200 mv pad_rxp/n inputs common mode voltage v icm - 600 - 1000 mv pad_rxp/n dc input impedance r ise single-ended 40 50 60 ? pad_rxp/n dc input impedance r id differential 80 100 120 ? pad_txp/n absolute output differential voltage (into floating 100 ? load) v od differential (peak-peak) 400 - 1000 mv pad_txp/n outputs common mode voltage v ocm - 400 600 900 mv pad_txp/n dc output impedance r ose single-ended 40 50 60 ? pad_txp/n dc output impedance r od differential 80 100 120 ? pad_txp/n short circuit current i short - -30 - 30 ma pad_ref_clk_p/n input differential voltage v idrefclk differential (peak-peak) 200 800 1600 mv pad_ref_clk_p/n inputs common mode voltage v cmrefclk - 1000 1200 1400 mv pad_ref_clk_p/n input impedance z refclk differential 70 100 130 ? frequency tolerance (clk_125, pad_clk_ref_p/n) clk 125mhz - -100 - +100 ppm input capacitance c in - - 5 - pf http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 36 of 58 rev 1.00 confidential - view under nda only 3.4 ac characteristics 3.4.1 system and serdes clocks timing table 19. system and serdes reference clocks timing description symbol min max unit clk_125, pad_ref_clk_p/n pulse width (high) t 1 3.6 4.4 ns clk_125, pad_ref_clk_p/n pulse width (low) t 2 3.6 4.4 ns clk_125, pad_ref_clk_p/n duty cycle - 40 60 % clk_125, pad_ref_clk_p/n clock period t 3 7.9992 8.0008 ns clk_125, pad_ref_clk_p/n total jitter (peak-peak) tj p-p - 40 ps clk_25 pulse width (high) t 1 18.0 22.0 ns clk_25 pulse width (low) t 2 18.0 22.0 ns clk_25 duty cycle - 45.0 55.0 % clk_25 clock period t 3 39.996 40.004 ns clk_125, pad_ref_cln_p/n (inputs), clk_25 (output) t1 t2 t3 figure 21. system and serdes clock timing http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 37 of 58 rev 1.00 confidential - view under nda only 3.4.2 local-side mii input timing of the 10/100 ethernet port table 20. local-side mii input timing of the 10/100 ethernet port description symbol min max unit mii_rxclk pulse width (high) (100mbps) 18.0 22.0 ns mii_rxclk pulse width (high) (10mbps) t 1 180.0 220.0 ns mii_rxclk pulse width (low) (100mbps) 18.0 22.0 ns mii_rxclk pulse width (low) (10mbps) t 2 180.0 220.0 ns mii_rxclk duty cycle - 40 60 % mii_rxclk clock period (100mbps) 36.0 44.0 ns mii_rxclk clock period (10mbps) t 3 360.0 440.0 ns mii_rxdv, mii_rxer, mii_rxd[3..0] setup to mii_rxclk rising edge t 4 10.0 - ns mii_rxdv, mii_rxer, mii_rxd[3..0] hold after mii_rxclk rising edge t 5 0.0 - ns mii_rxer, mii_rxdv, mii_rxd[n] mii_rxclk t1 t2 t3 t4 t5 figure 22. local-side mii input timing of the 10/100 ethernet port http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 38 of 58 rev 1.00 confidential - view under nda only 3.4.3 local-side mii output timi ng of the 10/100 ethernet port table 21. local-side mii output timing of the 10/100 ethernet port description symbol min max unit mii_txclk pulse width (high) (100mbps) 18.0 22.0 ns mii_txclk pulse width (high) (10mbps) t 1 180.0 220.0 ns mii_txclk pulse width (low) (100mbps) 18.0 22.0 ns mii_txclk pulse width (low) (10mbps) t 2 180.0 220.0 ns mii_txclk duty cycle - 40 60 % mii_txclk clock period (100mbps) 36.0 44.0 ns mii_txclk clock period (10mbps) t 3 360.0 440.0 ns mii_txen, mii_txer, mii_txd[3:0] setup to mii_txclk rising edge* t 4 10.0/ 15.0 - ns mii_txen, mii_txer, mii_txd[3:0] hold after mii_txclk rising edge* t 5 10.0/ 0.0 - ns * programmable value (phy/mac mode). mii_txer, mii_txen, mii_txd[n] mii_txclk t1 t2 t3 t4 t5 figure 23. local-side mii output timing of the 10/100 ethernet port http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 39 of 58 rev 1.00 confidential - view under nda only 3.4.4 local-side mii/gmii input timi ng of the 10/100/1000 ethernet port table 22. local-side mii/gmii input timing of the 10/100/1000 ethernet port description symbol min max unit gmii_rxclk pulse width (high) (100mbps) 18.0 22.0 ns gmii_rxclk pulse width (high) (10mbps) t 1 180.0 220.0 ns gmii_rxclk pulse width (low) (100mbps) 18.0 22.0 ns gmii_rxclk pulse width (low) (10mbps) t 2 180.0 220.0 ns gmii_rxclk duty cycle - 40 60 % gmii_rxclk clock period (100mbps) 36.0 44.0 ns gmii_rxclk clock period (10mbps) t 3 360.0 440.0 ns gmii_rxdv, gmii_rxer, gmii_rxd[3..0] setup to gmii_rxclk rising edge t 4 10.0 - ns gmii_rxdv, gmii_rxer, gmii_rxd[3..0] hold after gmii_rxclk rising edge t 5 0.0 - ns gmii_rxer, gmii_rxdv, gmii_rxd[n] gmii_rxclk t1 t2 t3 t4 t5 figure 24. local-side mii/gmii input timing of the 10/100/1000 ethernet port http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 40 of 58 rev 1.00 confidential - view under nda only 3.4.5 local-side mii/gmii output ti ming of the 10/100/1000 ethernet port table 23. local-side mii/gmii output timing of the 10/100/1000 ethernet port description symbol min max unit gmii_txclk pulse width (high) (100mbps) 18.0 22.0 ns gmii_txclk pulse width (high) (10mbps) t 1 180.0 220.0 ns gmii_txclk pulse width (low) (100mbps) 18.0 22.0 ns gmii_txclk pulse width (low) (10mbps) t 2 180.0 220.0 ns gmii_txclk duty cycle - 40 60 % gmii_txclk clock period (100mbps) 36.0 44.0 ns gmii_txclk clock period (10mbps) t 3 360.0 440.0 ns gmii_txen, gmii_txer, gmii_txd[3..0] setup to gmii_txclk rising edge* t 4 10.0/ 15.0 - ns gmii_txen, gmii_txer, gmii_txd[3..0] hold after gmii_txclk rising edge* t 5 10.0/ 0.0 - ns * programmable value (phy/mac mode). gmii_txer, gmii_txen, gmii_txd[n] gmii_txclk t1 t2 t3 t4 t5 figure 25. local-side mii/gmii output timing of the 10/100/1000 ethernet port http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 41 of 58 rev 1.00 confidential - view under nda only 3.4.6 local-side tbi/gmii input timing table 24. local-side tbi input timing description symbol min max unit tbi_rbc[1..0] clock pulse width (high) t 1 7.5 - ns tbi_rbc[1..0] clock pulse width (low) t 2 7.5 - ns tbi_rbc[1..0] clock duty cycle - 40 60 % tbi_rbc[1..0] clock period t 3 15.0 - ns tbi_rxd[9..0] setup to tbi_rbc[1..0] rising edge t 4 2.0 - ns tbi_rxd[9..0] hold after tbi_rbc[1..0] rising edge t 5 1.0 - ns tbi_rxd[n] tbi_rbc0 t1 t2 t3 t4 t5 tbi_rbc1 figure 26. local-side tbi input timing table 25. local-side gmii input timing description symbol min max unit gmii_rxclk pulse width (high) t 1 2.5 - ns gmii_rxclk pulse width (low) t 2 2.5 - ns gmii_rxclk duty cycle - 40 60 % gmii_rxclk clock period t 3 7.5 - ns gmii_rxdv, gmii_rxer, gmii_rxd[7..0] setup to gmii_rxclk rising edge t 4 2.0 - ns gmii_rxdv, gmii_rxer, gmii_rxdv, gmii_rxd[7..0] hold after gmii_rxclk rising edge t 5 0.0 - ns gmii_rxdv, gmii_rxer, gmii_rxd[n] gmii_rxclk t1 t2 t3 t4 t5 figure 27. local-side gmii input timing http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 42 of 58 rev 1.00 confidential - view under nda only 3.4.7 local-side tbi/gmii output timing table 26. local-side tbi/gmii output timing description symbol min max unit gmii_gtxclk/tbi_txclk pulse width (high) t 1 2.5 - ns gmii_gtxclk/tbi_txclk pulse width (low) t 2 2.5 - ns gmii_gtxclk/tbi_txclk duty cycle - 45 55 % gmii_gtxclk/tbi_txclk clock period t 3 7.5 8.5 ns gmii_txen, gmii_txer, gmii_txd[7..0], tbi_txd[9..0] setup to gmii_gtxclk/tbi_txclk rising edge t 4 2.5 - ns gmii_txen, gmii_txer, gmii_txd[7..0], tbi_txd[9..0] hold after gmii_gtxclk/tbi_txclk rising edge t 5 1.5 - ns gmii_txen, gmii_txer, gmii_txd[n], tbi_txd[n] gmii_gtxclk, tbi_txclk t1 t2 t3 t4 t5 figure 28. local-side tbi/gmii output timing http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 43 of 58 rev 1.00 confidential - view under nda only 3.4.8 ethernet serial ma nagement timing (mdio) table 27. ethernet serial management timing description symbol min max unit mdc pulse width (high) t 1 510.0 514.0 ns mdc pulse width (low) t 2 510.0 514.0 ns mdc clock period t 3 1.020 1.028 ns mdio (output) setup to mdc rising edge t 4 40.0 - ns mdio (output) hold time from mdc rising edge t 5 40.0 - ns mdio (input) setup to mdc falling edge t 6 20.0 - ns mdio (input) hold time from mdc falling edge t 7 20.0 - ns mdio (input) mdio (output) mdc t1 t2 t3 t4 t5 t6 t7 figure 29. mdio timing http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 44 of 58 rev 1.00 confidential - view under nda only 3.4.9 serdes timing table 28. serdes output timing description symbol min typ max unit pad_txp/n rise time t 1 100.0 - 200.0 ps pad_txp/n fall time t 2 100.0 - 200.0 ps pad_txp to pad_txn skew t 3 - - 50.0 ps serdes total transmit jitter tj e-12 1,2 - 67.3 152.0 1 ps serdes total transmit jitter tj p-p 2 - 43.0 - ps 1 defined at ber 10 -12 above 637khz as recommended by ieee draft p802.3ah tm /d3.3; section 60.6 (table 60-11 for tp1). 2 using lvpecl 125mhz oscillator with tj p-p of less than 40ps (pk-pk) for reference clock signals pad_ref_clk_p/n. figure 30. serdes output timing table 29. serdes input timing description symbol min typ max unit 3 serdes total input jitter tolerance tj e-12 1,2 0.749 1 - - ui serdes deterministic input jitter tolerance dj p-p 1,2 0.462 1 0.850 - ui 1 as recommended by ieee draft p802.3ah tm /d3.3; section 60.6 (table 60-10 for tp4). 2 using lvpecl 125mhz oscillator with tj p-p of less than 40ps (pk-pk) for reference clock signals pad_ref_clk_p/n. 3 ui = unit interval = 800ps for 1.25gbps; 400ps for 2.5gbps. http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 45 of 58 rev 1.00 confidential - view under nda only 3.4.10 spi timing table 30. spi timing description symbol min max unit spi_sclk pulse width (high) t 1 16.0 64.0 ns spi_sclk pulse width (low) t 2 16.0 64.0 ns spi_cs_n inactive time t 3 64.0 - ns spi_cs_n low to spi_sclk setup time t 4 12.0 - ns spi_ dout setup to spi_sclk rising edge t 5 12.0 - ns spi_ dout hold after spi_sclk rising edge t 6 12.0 - ns spi_ cs_n hold after spi_sclk falling edge t 7 28.0 - ns spi_ din setup to spi_sclk rising edge t 8 12.0 - ns spi_ din hold after spi_sclk rising edge t 9 12.0 - ns spi_sclk rising edge to spi_din high-z t 10 12.0 (t 1 +t 2 ) ns figure 31. spi write timing figure 32. spi read timing http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 46 of 58 rev 1.00 confidential - view under nda only 3.4.11 reset and clk_25 timing table 31. reset and clk_25 timing description symbol min max unit power on to rst_n high t 1 10.0 - ms rst_n pulse width t 2 1.0 - ms clk_25 valid before rst_n de-assertion t 3 500 - us clk_25 invalid after rst_n assertion t 4 - 200 ns figure 33. reset and clk_25 timing http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 47 of 58 rev 1.00 confidential - view under nda only 4 TK3715 physical dimensions 4.1 lqfp-128 package d pin 1 indicator exposed pad 1 38 39 64 65 102 103 128 d1 d d2 e e e1 e2 a p p q 1 q b b ccc c c seating plane c l1 a1 a2 a 0.05 - s (4x) c ddd a-b d s s bbb a-b d h aaa a-b d c (4x) l s r1 r2 gage plane 0.25mm q 2 q 3 h figure 34. lqfp-128 package drawing http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 48 of 58 rev 1.00 confidential - view under nda only table 32. lqfp-128 package dimensions reference min typ max unit a - - 1.60 mm a1 0.05 - 0.15 mm a2 1.35 1.40 1.45 mm d 22.00 bsc. mm d1 20.00 bsc. mm d2 18.50 mm e 16.00 bsc. mm e1 14.00 bsc. mm e2 12.50 mm r1 0.08 - - mm r2 0.08 - 0.20 mm q 0d 3.5o 7d mm q 1 0o - - mm q 2 11d 12.0o 13d mm q 3 11d 12.0o 13d mm c 0.09 - 0.20 mm l 0.45 0.60 0.75 mm l 1 1.00 ref mm s 0.20 - - mm p 8.00 - 8.10 mm b 0.17 0.20 0.27 mm e 0.50 bsc. mm aaa 0.20 mm bbb 0.20 mm ccc 0.08 mm ddd 0.08 mm notes: 1. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 2. dimension ? b ? does not include dambar protrusion. allowable dambar protru sion shall not cause the lead width to exceed the maximum ? b ? dimension by more than 0.08mm. 3. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm. http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 49 of 58 rev 1.00 confidential - view under nda only 4.1.1 lqfp-128 exposed pad pcb design guidelines the TK3715 lqfp-128 package has an ex posed pad at the bottom to provide the primary heat removal path. it also provides grounding to the printed circuit board (pcb). the exposed pad allows reduction of the loop inductance, providing an excellent grounding method for high frequency applications. the exposed pad must be soldered directly to the pcb to benefit from the improved thermal and electrical behavior. a land pattern must be incorporated on the pcb within the footprint of the package. the land pattern must correspond to the exposed metal pad on the package. refer to figure 35. figure 35. recommended land pattern the land pattern on the pcb performs the heat transfer and the electrical grounding from the package to the board. this is done through a solder joint. thermal vias and/or the plated hole (solder port) are required to effectively conduct heat from the surfac e of the pcb to the ground plane(s). these vias and/or the plated hole act as ?heat pipes.? in some cases, only thermal vias are used to connect the exposed pad to the underlying ground planes. in these cases, an array of vias must be incorporated on the land pa ttern at 1.0 to 1.5mm grid. this will achieve maximum thermal and electrical performance. refer to figure 36. it is recommended that the array of vias is constructed with at least 25 vias . teknovus also recommends that via diamet er be 0.30 to 0.35mm, with at least 0.5 oz. copper via barrel plating. http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 50 of 58 rev 1.00 confidential - view under nda only recommended stencil openings 1.0-1.5mm 0.2-0.3mm 0.8-2.5mm figure 36. recommended vias grid dimensions and stencil openings the thermal vias and the plated hole together provide a superior thermal and electrical solution. they also improve re-manufacturing capabilities. in this solution, t he array of vias can be incorporated on the land pattern at 1.0 to 1.5mm grid. the plated hole should have a 2.5mm diameter. refer to figure 37. via diameter should be 0.30 to 0.35mm, with at least 0.5 oz. copper via barrel plating. recommended stencil openings plated hole ( ? 2.5mm) 1.0-1.5mm 0.2-0.3mm 1.0-1.5mm figure 37. vias and plated hole dimensions http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 51 of 58 rev 1.00 confidential - view under nda only solder paste must be applied to both the exposed pa d of the TK3715 package and the land pattern on the pcb. this will ensure proper soldering. the package stand- off must be considered when determining the stencil thickness. for a nominal stand-off of 0.1mm, teknovus recommends a stencil thickness of 0.125 to 0.200mm. a large stencil opening may result in poor release. therefore, the aperture opening should be subdivided into an array of smaller openings of less than 2.5mm. refer to t he black areas in figure 36 and figure 37. the guidelines above enable the solder joint area to be 80% to 90% of the exposed pad area. http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 52 of 58 rev 1.00 confidential - view under nda only 4.2 tfbga-169 package figure 38. tfbga-169 package drawing http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 53 of 58 rev 1.00 confidential - view under nda only table 33. tfbga-169 package dimensions reference symbol common dimension unit package type - tfbga - ball count n 169 - x e 11.000 mm body size y d 11.000 mm x ee 0.800 mm ball pitch y ed 0.800 mm total thickness a 1.200 max. mm mold thickness m 0.530 ref. mm substrate thickness s 0.360 ref. mm ball diameter - 0.350 mm stand off a1 0.220 ~ 0.320 mm ball width b 0.320 ~ 0.420 mm package edge tolerance aaa 0.150 mm mold flatness bbb 0.200 mm co-planarity ccc 0.080 mm ball offset (package) ddd 0.150 mm ball offset (ball) eee 0.080 mm x e1 9.600 mm edge ball center to center y e1 9.600 mm http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 54 of 58 rev 1.00 confidential - view under nda only 5 TK3715 ordering information figure 39. TK3715 ordering information http:///
TK3715 data sheet turbo-epon tm soc bridge for china standard onu page 55 of 58 rev 1.00 confidential - view under nda only notice a data sheet is a technical document that describes the func tionality of a device or component, including the electrical characteristics, packaging, and signal conne ctions. in the semiconductor industry, data sheet information develops as the product progresses through it s life-cycle. therefore, in accordance with industry standards, teknovus categorizes its data sheets as follows: ? product preview ? a product preview documents the current state of a new product or concept. functional definitions may be included, but all information is subject to change, including the company?s commitment to develop and manufacture the product. changes are not subject to product change notification. ? advance information ? advance information refers to the data sheet for a product that is in design or early prototyping. the data sheet includes the pi n-out or ball-out and package definition, but these definitions may change due to evolving design, function, or timing requirements. all ac or dc operating parameters are subject to change, pending device characterization. changes are communicated to customers via emailed product change notifications. ? preliminary ? a preliminary data sheet describes a devic e that is in the early stages of volume manufacturing. ac and dc operating parameters are subject to change, pending further characterization of multiple wafer lots. changes are communicated to customers via emailed product change notifications. ? no label ? contents of an unlabeled data sheet sh ould be stable, although contents may be updated due to refined characterization, bug discovery, and manufacturing issues. changes are communicated to customers via emailed product change notifications. to ensure receipt of these not ifications, you must be registered with teknovus? customer support system. please visit our website at www.teknovus.com , click login , and follow the displayed instructions. if you are not currently registered, click contact us to locate the office in your region. teknovus inc. 1351 redwood way petaluma, ca 94954 for more information or to find your local office, visit our website at: www.teknovus.com http:///

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